IBM sub-1nm chip technology (nanostack)

IBM's sub-1 nm chip technology is a semiconductor research result announced on 25 June 2026 at the 0.7 nm (7 angstrom) node. It is built on "nanostack", which IBM describes as the industry's first known three-dimensional, nanosheet-based transistor design. Nanostack vertically stacks and staggers transistors using 3D sequential integration and allows different material combinations in each stacked layer.

IBM says the chip packs nearly 100 billion transistors onto a fingernail-sized die, nearly twice the density of its 2 nm chip unveiled in 2021. Published technical results project up to 50% more performance or 70% greater energy efficiency compared with IBM's 2 nm node chips. Research presented at VLSI 2026 reported 40% scaling in SRAM. Experimental validation covered ultra-thin dielectric bonding in CMOS integration, dual-channel engineering and a functional CMOS inverter. The performance figures are projections.

This is a research demonstration, not a purchasable product. IBM says it sees a path to production as early as the next 5 years. The work is done with partners at the Albany, New York research facility, including Lam Research, Tokyo Electron and SCREEN, on High NA EUV processes using ASML tooling. IBM notes that node names refer to a manufacturing generation rather than an exact physical dimension.